We’re keeping the momentum strong! This week, the dev team has been working behind the scenes on GPU and FPGA acceleration for Expander.
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BN254 Pipeline Optimization: Completed the refactoring of BN254 arithmetic logic on FPGA, optimizing pipeline depth and balancing latency across adders and multipliers. Achieved stable timing closure at 260 MHz, improving arithmetic throughput.
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LinearGKR Hardware Refinement: Enhanced the dual-phase prepare operator by introducing fine-grained pipeline segmentation and memory reuse between the two stages. This reduced BRAM utilization by over 20% while maintaining full concurrency.
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Next Integration Phase: Began integrating the optimized FPGA LinearGKR modules into the full GKR proof pipeline, preparing for end-to-end hardware verification and unified GPU–FPGA co-design testing.
Stay tuned for more updates.
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